This invention relates to a drive circuit for a liquid crystal display device, and more particularly, to a drive circuit for a liquid crystal television receiver.
A known liquid display device has scanning electrodes and signal electrodes provided for liquid crystal elements arranged in a matrix, and uses a scanning electrode driver and a signal electrode driver to drive these electrodes in order to display an image based on input data.
An example of such a conventional liquid crystal display device is disclosed in NIKKEI ELECTRONICS, 1984 9-10, PP. 233-236. This device has a liquid crystal display having a plurality of liquid crystal elements arranged in a matrix. For each liquid crystal element, a signal electrodes X.sub.1, X.sub.2, . . . , and X.sub.n and a scanning electrodes Y.sub.1, Y.sub.2, . . . , and Y.sub.m are provided. For example, liquid crystal element L.sub.1 is coupled to signal electrode X.sub.1 and scanning electrode Y.sub.1 in the following manner. Signal electrode X.sub.1 and scanning electrode Y.sub.1 are respectively coupled to the drain and gate of a thin-film transistor (TFT). The source of the TFT is grounded through a signal accumulation capacitor C.sub.1 and also coupled to one terminal of liquid crystal element L.sub.1, which has the other terminal coupled to a common electrode.
A liquid crystal display device having the afore-mentioned liquid crystal display processes a signal received by an antenna and provides a video signal whose polarity changes for each field. The received signal is also processed to provide a clock and a data pulse, which are supplied to the signal eleotrode driver and scanning electrode driver.
The signal electrode driver, which is also called an X driver, comprises, for example, shift register and receives a horizontal sync signal H (15.75 KHz) as well as the clock and the data pulse. The scanning electrode driver, which is also called a Y driver, also comprises shift register, for example. The scanning electrode driver receives a vertical sync signal V (60 Hz) in addition to the clock and the data pulse.
The signal electrode driver also has a switch circuit which receives the video signal. The switch circuit includes switch means S.sub.1, S.sub.2, . . . , and S.sub.n, whose input terminals are supplied with the video signal and whose output terminals are respectively coupled to signal electrodes X.sub.1, X.sub.2, . . . , and X.sub.n. The activation of these switch means S.sub.1 -S.sub.n is controlled by the shift register.
In the liquid crystal display device having the above structure, scanning electrodes Y.sub.1 -Y.sub.m are sequentially driven in synchronization with one horizontal scanning period (1H) of the video signal. During this period, switch means S.sub.1 -S.sub.n respectively coupled to signal electrodes X.sub.1 -X.sub.n are activated, thus supplying signals to the associated signal accumulation capacitors C.sub.1 -C.sub.n. The supplied signals respectively energize liquid crystal elements L.sub.1 -L.sub.n until the scanning of the next frame.
In the liquid display device, provided that the number of pixels of the liquid crystal display in the X direction (lateral direction) is N, the number of the switch means (S.sub.1 -S.sub.n) required is also N. Typical switch means are C-MOS analog switches.
Since each switch means has an input capacitance, the input capacitance C of the switch circuit is EQU C=N.multidot.C.sub.0,
where C.sub.0 is the input capacitance of each switch means S.sub.1, . . . , or S.sub.n. Therefore, the greater the number of the pixels provided by the liquid crystal elements, the greater the input capacitance of the switch circuit. To cope with this problem, a buffer circuit is provided on the prior stage to the switch circuit. The buffer circuit is constituted, for example, by a transistor which has a base supplied with a video signal, an emitter grounded through a constant current source I and a collector coupled to a power source Vcc. The switch circuit is coupled to the emitter of the transistor.
Since the buffer circuit drives a load having a capacitance C, it is necessary to supply a current above a certain value to constant current source I. Assuming that the amount of the current is I, then EQU I&gt;2.pi.fCV,
where f is the maximum frequency of a signal and V is the maximum amplitude of the signal.
Therefore, the dissipation power P of the buffer circuit is EQU P&gt;Vcc I.
As a compact or portable liquid crystal display device is designed to be battery-driven, an increase in the capacitance C (the dissipation power) is fatal and should be avoided.
Provided that the number of switch means S.sub.1 -S.sub.n is n=400 and the input capacitance C.sub.0 of each switch means is 1 pF, this yields EQU C=N.multidot.C.sub.0 =400 .times.1 =400 pF.
However, an input video signal is adversely influenced even when the capacitance C is about 100 pF. In this respect, it is desirable to reduce the input capacitance C.